1. Field of the Invention
This invention relates to the field of electronic circuit design and in particular to an apparatus and method for specifying and testing a plurality of power and ground domains within an electronic circuit design.
2. Discussion of Related Art
There are several levels of electronic circuit design to design devices of varying sophistication. At a basic level, devices are modeled at the transistor level. Signals are described in terms of voltage levels, such as, 0 v, 3.36 v, 5 v. At the next design level, devices are modeled at the gate level. Here, transistor level devices are integrated, for example, as AND and OR boolean function logic gates. At this level, voltages are not explicitly described but rather logic levels of 0 or 1 or simulated. At the next higher design level, gate level devices are integrated to form integrated circuit (also referred to herein as IC). At this level, the most primitive or low-level component is the IC with a behavior description used for simulation. The highest design level is system design, where the components are boards or subsystems. Here the most primitive components are modeled using behavior descriptions.
Electronic circuit designers design and test the performance of electronic circuit designs using various tools. Computer Aided Design (CAD) tools (also commonly referred to as Computer Aided Engineering or CAE tools) are used to create, test, edit, and verify the performance of the electronic circuit design. CAD tools create a description of an electronic circuit design in the form of a design database having design information shared by the various tools in the CAD/CAE toolset. The tools of the CAD/CAE toolset include programs which allow a user to edit and review the electronic circuit design as described in the design database. The information in the design database can be presented to the user in graphical form, for example, a schematic wherein a graphical icon represents each device in the electronic circuit design. Interconnecting lines represents the interconnections between devices.
The information in the database can also be presented to the user in textual form in a list of the various interconnections between the devices in the electronic circuit design. This list is often referred to as a netlist, and can be represented as a tabular listing of the devices in the electronic circuit design. Each row (entry) of the table describes particular input and output signals of the device and the connection of those signal paths to other signal paths of other devices. The netlist includes a cell name for each device within the electronic circuit design. The cell name is typically the same name given to the equivalent device stored in a library database of devices available for use by the CAD/CAE tools. Other industry standard netlist formats include Verilog, EDIF, DEF and TDL. While these formats contain the same basic information as that of a tabular listing, these netlist formats are considered to be "languages" having well defined syntax and semantics which allow CAD tools to reliably exchange them for interaction among the tools.
Netlist or schematic views of an electronic circuit design are generally stored in or derived from the information stored in the design database. Thus, a tool which requires a netlist or schematic does so by extracting the required information from the design database and outputting the required list or graphical representation.
Table 1 below provides an example of a netlist for a simple exemplary electronic circuit design. As shown in FIG. 1A, a first AND Gate (U1) has inputs A and B and output D. A second AND Gate (U2) has an input D from the first AND Gate (U1), input C, and output E. As shown in Table 1, each individual AND Gate is separately identified by a cell name or type (usually equivalent to its library name in the design database of components used by the CAD/CAE tools) and by an instance identifier. The instance identifier is useful for distinctly identifying individual components within the circuit design. For example, the instance is useful for identifying the first AND Gate from the second AND Gate.
TABLE 1 ______________________________________ Name of Cell Instance Cell Name/Type Input Signals Output Signals ______________________________________ U1 AND Gate A, B D U2 AND Gate C, D E ______________________________________
Table 1 and FIG. 1A, are examples of a trivial electronic circuit design. It is known in the art to integrate low-level or "primitive" designs to design devices of varying sophistication which obtain better performance, lower power consumption, etc. As the need increases for creating smaller and faster products, more components are being integrated into ICs. It is common to integrate pre-defined higher level circuit designs with other pre-defined high level electronic circuit designs to further increase the level of integration. Often such high level pre-defined circuits are referred to as "cells" or "standard cells." The process of designing an electronic circuit using such cells is often referred to as standard cell design. CAD/CAE tools which provide standard cell design capabilities generally include a library of standard cell designs which the user may select to create a new higher level electronic circuit design.
For example, it is now common that very complex standard cells are predefined in standard cell libraries, such as, cache memory which stores data within a computer, or a central processing unit (hereinafter referred to as the CPU). A final circuit design is comprised of the interconnection of such higher-level components, such as the cache memory, bus logic, CPU, etc.
Electronic circuit designs (e.g., standard cell circuit designs) which include various high level ICs, lower level ICs, and simple discrete devices may require multiple power and ground connections to a particular device for proper operation. Such multiple power and ground paths (also referred to as power domains) are useful for many purposes including: use of sophisticated power management schemes, isolation of sections of logic powered by battery-backup, electronic noise reduction, and simplification of testing.
The number of power and ground domains depends upon the particular problem the electronic circuit designer is solving. For example, an electronic circuit designer may want to isolate sections of a circuit from other power sources. Similarly, an electronic circuit designer may group the cells on the periphery of an IC (these cells provide the off-chip input/output signals and power and ground sources to the IC) that are associated with particular power sources and isolate these cells from other power and ground sources.
Electronic circuit designers creating entire circuit board designs that contain multiple ICs are also confronted with similar design requirements for multiple power and ground connections. In this case, the designer must provide a multiple number of power and ground domains to a group of devices, such as ICs, on the electronic circuit board. It is known to explicitly describe each of these signals in a board netlist and show the connectivity in the schematic. This method, however, is burdensome to the electronic circuit designer with the increasing number of components on boards and within the entire system.
As presently known in the art at the standard cell or IC design level, there are no explicit power and ground pins described or modeled for each cell. Instead, standard cells or ICs are assumed to be connected to a common power and ground for the entire design. Most netlist languages refer to this common power signal by a pre-defined name which represents a logical "1." Likewise the common ground signal is represented by a predefined signal name that represents a logical "0."
For the purpose of gate level or IC simulation, multiple power and ground signals serve no purpose. Since the standard cells are modeled assuming proper power and ground connection to every device, the power and ground signal pins are not in most modern standard cell libraries.
No one mechanism exists to automatically describe within the design database (e.g., in a netlist), multiple power domains from the transistor level to the board level. Presently, CAD/CAE tools do not provide a set of tools that easily allows identification of related groups of devices for association with multiple power and ground domains at the transistor, standard cell or IC level, and board levels. Consequently, these CAD/CAE tools cannot easily create, test, or simulate the design of a complex electronic circuit design with regard to multiple power and ground domains.
An informal solution to the above problems is presently practiced in the art and involves verbal communication of such multiple power and ground information among engineers outside the context of the CAD/CAE toolset features. For example, a layout engineer typically arranges the floorplan (the physical placement) of the electronic circuit design in a graphical floorplanning tool by selecting the location of the components and signal lines of the electronic circuit design using a schematic and/or netlist annotated with such verbal communication. The design engineer may communicate orally or in written annotations associated with the design as to preferred positioning as it may relate to preferred power and ground connections and groupings. Such manual communication techniques frequently introduce errors because information useful to the various CAD/CAE tools is manually transcribed and entered from the verbal communications. Since multiple power and ground connections are not currently stored within the netlist (the design database), annotations on the schematic may be implemented incorrectly because the layout engineer may incorrectly interpret the circuit designer's instructions or the instructions may be incomplete.
An alternative approach is to modify every cell in the standard cell library to make the power and ground pins explicit. In other words, the cell definition may force the design engineer to describe explicitly the connection of every power and ground signal associated with a particular cell or circuit which is included in the circuit design. Such a restriction adds significant costs due to updates required in the standard cell libraries and places an additional burden on the electronic circuit designer to explicitly connect every cell to a power and ground path in the netlist. Complex electronic circuit designs may contain hundreds of thousands of cells. The requirement to explicitly connect power and ground signals for each such cell can therefore represent a significant cost on every design. For example, as shown in FIG. 1B, cell U1 and U2 has two more additional pins (e.g., p and g) where the power pin "p" is connected to UDP and the ground pin "g" is connected to VSS.
It is evident from the above discussion that a need exists for an apparatus and method to define multiple power and ground domains within a circuit design to facilitate automatic checking and distribution of power and ground signals without imposing the severe overhead on the user of explicitly connecting every cell in the netlist to power and ground. Further, as noted above, it is preferable that such a method and apparatus be useful for specifying power and ground connections and many levels of electronic design from low level designs through board or system level designs.